Chapter 18: Interfaces Library
Table 18–3 lists the signals supported by the Avalon-MM Slave block.
Table 18–3. Signals Supported by the Avalon-MM Slave Block
18–5
Signal
address
read
readdata
write
writedata
byteenable
readyfordata
dataavailable
endofpacket
readdatavalid
waitrequest
beginbursttransfer
burstcount
irq
begintransfer
chipselect
Direction
Output
Output
Input
Output
Output
Output
Input
Input
Input
Input
Input
Output
Output
Input
Output
Output
Description
Address lines to the slave port. Specifies a word offset into the slave address
space.
Available when Read or Read/Write address type is chosen. Read-request
signal. Not required if there are no read transfers. If used, also use readdata .
Available when Read or Read/Write address type is chosen. Data lines for read
transfers. Not required if there are no read transfers. If used, also use read .
Available when Write or Read/Write address type is chosen. Write-request
signal. Not required if there are no write transfers. If used, also use writedata .
Available when Write or Read/Write address type is chosen. Data lines for write
transfers. Not required if there are no write transfers. If used, also use write .
Available when Allow Byte Enable is on and the bit width is greater than 8.
Byte-enable signals to enable specific byte lane(s) during write transfers to
memories of width greater than 8 bits. If used, also use writedata .
Available when Write or Read/Write access is chosen and Allow Flow Control is
on. Indicates that the peripheral is ready for a write transfer.
Available when Read or Read/Write access is chosen and Allow Flow Control is
on. Indicates that the peripheral is ready for a read transfer.
Available when Allow Flow Control is on. Indicates an end-of-packet condition.
Available when Allow Pipeline Transfers is on and variable read latency is
chosen. Marks the rising clock edge when readdata asserts.
Available when variable wait-state format is chosen. Use to stall the interface
when the slave port cannot respond immediately.
Available when Allow Burst Transfers is on. Asserted for the first cycle of a burst
to indicate when a burst transfer is starting.
Available when Allow Burst Transfers is on. Indicates the number of transfers in
a burst. If used, also use waitrequest .
Available when Output IRQ is on. Interrupt request. Asserted when a port needs
to be serviced.
Available when Receive Begin Transfer is on. Asserted during the first cycle of
every transfer.
Available when Use Chip Select is on. The slave port ignores all other
Avalon-MM signal inputs unless chipselect is asserted.
1
The direction in Table 18–3 refers to the direction in respect of the DSP Builder block
interface.
Table 18–4 shows the Avalon-MM Slave block parameters.
Table 18–4. Avalon-MM Slave Block Parameters
Name
Specify Clock
Clock
Address Width
Value
On or Off
User defined
1–32
Description
Turn on to explicitly specify the clock name.
Specifies the clock signal name.
Specifies the number of address bits.
November 2013
Altera Corporation
DSP Builder Handbook
Volume 2: DSP Builder Standard Blockset
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